1. Field of the Invention
This invention is in the field of Phase-Locked Loops (hereafter "PLLs") and methods of operation therefore and, more particularly, is a Phase-Locked Loop (hereafter "PLL") having improved locking times and a method of operation therefore.
2. Description of the Related Art
Phase-locked loops are well known to those skilled in the art of electrical engineering. In its most basic form, a PLL is simply a closed loop feedback system designed to drive the feedback signal to match the input reference signal in both phase and frequency. Typically, a system incorporating a PLL uses the PLL to generate a signal of a desired frequency for use by the system. In particular, the reference signal input to the PLL is changed in frequency and/or phase, and in response, the PLL drives the feedback signal to match the input reference signal in phase and frequency. Once matched, the feedback signal can be used by the system.
While the feedback signal is transient (i.e., from the time that the reference signal input changes until the feedback signal has approximately reached the reference signal in phase and frequency), a charge pump of the PLL either adds or removes charge from capacitors in a Low Pass Filter (hereafter "LPF"). The potential output from the LPF is input to a Voltage Controlled Oscillator (hereafter "VCO") who's output signal provides via a scaling factor, if necessary, the feedback signal. Generally, the frequency of the output signal from the VCO is proportional to the VCO's input voltage. Accordingly, the quicker that the PLL is able to charge, or discharge as the case may require, the capacitors in the LPF to the potential corresponding to the desired frequency for the feedback signal, the shorter, and therefore better, the locking time will be for the PLL. The term, "locking time," refers to the time required for the feedback signal to reach the frequency and phase of the input reference signal after a change in the input reference signal.
Shorter locking times are generally desirable for PLLs. However, due to the inherent nature of one of the PLL's components, locking times are unfortunately, relatively long. More specifically, a modern day PLL includes a Phase Frequency Detector (hereafter "PFD"). The operation of a standard PFD, which like all of the aforementioned components in a standard PLL, is well known to those skilled in the art, and it causes unnecessarily long locking times for the PLL.
To facilitate a better understanding of this proposition, one must first understand the general operating characteristics of a PFD within a PLL. In particular, a PFD has as inputs the reference and feedback signals. The PFD compares these signals in order to determine if the feedback signal is running slower, faster, or at the same frequency and phase as the reference signal. If the feedback signal is running slower, the PFD asserts a signal generally referred to as an UP signal, which via PLL operation, ultimately results in the feedback signal speeding up. Assertion of the UP signal causes the charge pump to add charge to the capacitors in the LPF, thereby speeding up the feedback signal. Conversely, if the feedback signal is running faster than the reference signal, the PFD asserts a signal generally referred to as a DOWN (sometimes abbreviated as DWN) signal, which via PLL operation, ultimately results in the feedback signal slowing down. Assertion of the DWN signal causes the charge pump to remove charge from the capacitors in the LPF, and this results in slowing the feedback signal. Lastly, when the reference and feedback signals are monitored in phase and frequency, the PLL is locked, so both the UP and DWN signals are de-asserted, causing the charge pump to neither add nor remove charge from the LPF, thereby not changing the feedback signal.
Now, in light of the foregoing discussion, it should be apparent that anything that slows the process of charging, or discharging as the case may be, the capacitors in the LPF causes increased locking times for the PLL. The PFD, due to its inherent operational nature, slows the charging of the LPF capacitors in the case where the feedback signal is running slow. In order to explain, assume that the feedback signal is running slower than the reference signal, which means that a given rising edge of the reference signal will be detected by the PFD before a corresponding rising edge for the feedback signal. When the reference signal's rising edge is detected, the PFD will assert its UP signal causing more charge to be added to the LPF's capacitors, and the frequency of the feedback signal to rise--the desired effect. Soon thereafter though, a rising edge of the lagging feedback signal will be detected, and at this point, the PFD asserts the DOWN signal, but for only a short time since the PFD resets itself (i.e., de-asserts both the UP and DOWN signals) when both have been asserted. Thus, when the DWN signal de-asserts, the UP signal also will de-assert per the standard operation of a PFD. Of course, when the UP signal is de-asserted, the addition of charge to the LPF's capacitors from the charge pump will be interrupted until the UP signal is again asserted by the detection of the next rising edge of the reference signal by the PFD. This interruption of charging to the LPF results in longer locking times for the PLL; however, due to the intrinsic operational characteristics of the PFD, it is unavoidable.
Therefore, there existed a need to provide a PLL having supplemental charging and discharging circuitry for improving PLL locking times and a method of operation therefore.